The present invention relates to a chip type solid electrolytic capacitor and to a method of manufacturing the same.
An example of a chip type solid electrolytic capacitor comprises a capacitor element, a packaging resin covering the capacitor element, and anode and cathode terminal which are electrically connected to the capacitor element and coupled to the packaging resin. The packaging resin has a mount surface and a side surface adjacent to the mount surface. A chip type solid electrolytic capacitor of the type is disclosed in Japanese Unexamined Patent Application Publication No. 291079/1993 and will be described in detail in conjunction with the drawing.
In case where such a chip type solid electrolytic capacitor is tried to be reduced in size and in height, a volume ratio of the anode and the cathode terminals relative to the chip type solid electrolytic capacitor is increased. When the volume ratio of the anode and the cathode terminals is increased, the ratio of the volume of a portion of the capacitor element which contributes to capacitance with respect to the total volume of the capacitor, i.e., the volume efficiency is reduced. For example, when the thickness (height) of the capacitor (the package resin) is 0.8 mm, the volume efficiency of capacitor element may be as small as 20% or less.